1. Field of the Invention
The subject matter of this disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to a technique for forming inter-level conductive connections and for monitoring this process in semiconductor devices comprising one or more metallization layers.
2. Description of the Related Art
In an integrated circuit, a large number of circuit elements, such as transistors, capacitors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of many modern integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but such electrical connections may be established in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnections. In this specification, unless otherwise specified, a contact connecting to a circuit element or a portion thereof, for example, a gate electrode or a drain or source region of a transistor, may also be considered as an inter-level connection.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases. The increased packing density usually requires an even greater increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers involves extremely challenging issues to be dealt with.
For example, copper and alloys thereof are metals generally used for sophisticated applications due to high conductivity and less electromigration effects compared to aluminum, which has been used over the last decades. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and copper also may not be effectively patterned by the usually employed anisotropic etch procedures. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used wherein a dielectric layer is first blanket-deposited and then patterned to define trenches and vias, which are subsequently filled with copper or copper alloys.
A further major drawback of copper is its tendency to readily diffuse in silicon dioxide and other low-k dielectrics. It is therefore usually necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially reduce diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. The barrier material provided between the copper and the dielectric material should, however, in addition to the required barrier characteristics, exhibit good adhesion to the dielectric material as well as to the copper and copper alloys and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnection as typically the barrier material's electric resistance is significantly greater than the electric resistance of copper and many of the copper alloys. In typical copper-based applications, tantalum and tantalum nitride, alone or in combination, as well as titanium and titanium nitride, alone or in combination, may be successfully employed as barrier layers. However, any other barrier layer schemes may be used as long as the required electrical, diffusion hindering and adhesion characteristics are obtained.
Irrespective of the material used for the barrier layer, with steadily decreasing features sizes, process engineers are increasingly confronted with the challenging task to form respective openings in the dielectric layer and deposit an extremely thin barrier layer within these openings having significantly high aspect ratios of approximately 5 or more for a trench width or a via diameter of about 0.2 μm and even less. The thickness of the barrier layer has to be chosen as thin as possible so as to not unduly consume “precious” space of the interconnection that should be filled with the more conductive copper, yet reliably suppress or prevent the diffusion of the copper into the neighboring dielectric. On the other hand, the etch process for forming the via openings is very critical as, on the one side, the opening has to reliably “land” on, i.e., connect to, the underlying metal or semiconductor region, if a contact opening is considered, while, on the other side, the “consumption” of metal or conductive material is to be maintained at a low level, when etching into the metal or conductive region, since even after re-filling the via or contact opening, the barrier material may increase the overall resistivity of the underlying metal. In particular, for highly scaled semiconductor devices, a high degree of uniformity of corresponding interconnect structures and contact vias is important, since any variation in resistance and thus current density may lead to fluctuations during operating the device and may even result in a premature failure of the device.
With reference to FIG. 1, the problems involved in forming a via to underlying metal regions and other conductive regions may be described in more detail. In FIG. 1, a semiconductor structure 100 comprises a substrate 101, which is to represent any appropriate substrate for the formation of microstructures including conductive and insulating areas, wherein at least some of the conductive areas are used for flowing a current through the semiconductor structure 100. For example, the substrate 101 may comprise a plurality of circuit elements of an integrated circuit, the electrical connection of which may require the formation of one or more “wiring” layers for providing the specified functionality of the integrated circuit. For convenience, any such circuit elements, such as transistors, capacitors and the like, are not shown. Formed above the substrate 101 is a conductive region 102, such as a contact region of a transistor, a capacitor and the like, so that the conductive region 102 may represent a highly doped semiconductor region, a semiconductor region including a metal silicide and the like. In other cases, the conductive region 102 may represent a metal line or any other metal region according to specific design criteria. For example, as previously pointed out, in highly scaled integrated circuits, copper or copper-based metals are frequently used for forming highly conductive metal regions. The conductive region 102 may be embedded in a dielectric material 104, which may be comprised of any appropriate material, such as silicon dioxide, silicon nitride, low-k dielectrics and the like.
A dielectric layer 103 comprised of any appropriate material or material composition, such as silicon dioxide, silicon nitride, low-k dielectric materials and the like, is formed above the metal region 102, wherein an etch stop layer 106 is provided between the metal region 102 and the dielectric layer 103. The etch stop layer 106 may be comprised of any appropriate material that exhibits high etch selectivity with respect to the material of the dielectric layer 103 so as to allow efficient control of an etch process through the dielectric layer 103. For example, silicon nitride, silicon carbide, nitrogen-enriched silicon carbide, silicon dioxide and the like may be appropriate materials for the etch stop layer 106. Moreover, a via opening 103A is formed in the layer 103 and may extend to a certain degree into the etch stop layer 106, wherein the via opening 103A is to be filled with a highly conductive material, such as metal and metal compounds and the like, in a later stage after completely etching through the etch stop layer 106. As previously explained, if a highly conductive material, such as copper or a copper alloy, may be used for filling the via opening 103A, in combination with a barrier material having a significantly lower conductivity, which may be present at the bottom of the respective via, the resulting electrical resistance of the conductive region 102, in combination with the resulting via, may depend on the degree of material consumption of the etch stop layer 106 caused by an etch process. Hence, the recess formed in the etch stop layer 106 at this manufacturing stage may significantly affect the overall performance of the resulting interconnect structure.
During the formation of the semiconductor device 100 as shown, after providing the layers 106 and 103 based on established techniques, respective lithography processes are performed to provide an appropriate etch mask. Thereafter, an anisotropic etch process is performed on the basis of a specified etch recipe, which depends on the material composition of the dielectric layer 103 and other device and process requirements. The anisotropic etch front has to be reliably stopped in the etch stop layer 106 to compensate for any across-substrate variations, for different intended etch depths, if required, or for substrate-to-substrate variations. On the other hand, a certain degree of material removal may be desirable to relax any constraints for the subsequent phase or step of the etch process for opening the etch stop layer 106 so as to not unduly remove material from the region 102. In a subsequent etch process, the etch stop layer 106 may be opened, wherein a reliable connection from the via opening 103A into the conductive region 102 is required. Depending on the uniformity of the previous etch process, the etch selectivity of the layer 106, the uniformity of the subsequent etch process for opening the layer 106 and other process non-uniformities, the amount of etching into the conductive region 102 may vary, thereby contributing to the non-uniformities of the electrical performance of the device 100.
Thus, it is important to monitor the etch rate during the respective etch process, since the performance of a respect etch tool may significantly vary, in particular at respective wet clean processes that may be performed on a regular basis during maintenance activities and the like. Therefore, in conventional monitoring of process strategies, the etch rate of the etch stop layer is determined by using SEM (scanning electron microscopy) and/or TEM (transmission electron microscopy) images of cross-sections obtained from dedicated test wafers having formed thereon a moderately thick etch stop layer 106. However, this procedure requires a great deal of effort in preparing appropriate samples. Moreover, it is a destructive measuring technique and thus provides only low statistics, which may therefore reduce the reliability of the measurement results. Moreover, the entire measurement procedure including the preparation of samples is very slow and thus may limit the ability to provide an efficient process control.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.